Neuromorphic architectures for nanoelectronic circuits

This paper reviews recent important results in the development of neuromorphic network architectures (‘CrossNets’) for future hybrid semiconductor=nanodevice-integrated circuits. In particular, we have shown that despite the hardware-imposed limitations, a simple weight import procedure allows the CrossNets using simple two-terminal nanodevices to perform functions (such as image recognition and pattern classi cation) that had been earlier demonstrated in neural networks with continuous, deterministic synaptic weights. Moreover, CrossNets can also be trained to work as classi ers by the faster error-backpropagation method, despite the absence of a layered structure typical for the usual neural networks. Finally, one more method, ‘global reinforcement’, may be suitable for training CrossNets to perform not only the pattern classi cation, but also more intellectual tasks. A demonstration of such training would open a way towards arti cial cerebral-cortex-scale networks capable of advanced information processing (and possibly self-development) at a speed several orders of magnitude higher than that of their biological prototypes. Copyright ? 2004 John Wiley & Sons, Ltd.